1. Field of the Invention
The present invention relates generally to semiconductor device. More particularly, the invention relates to a semiconductor device having improved high-frequency characteristics, and a method of fabricating the device.
2. Description of the Related Art
In recent years, communication devices, such as cellular phones, portable telephones designed for the Personal Handy Phone System (PHS), and Personal Digital Assistants (PDAs), have been very popular and used extensively worldwide. Under such circumstances, there has been the need to provide low-price communication devices capable of faster and larger-capacity communication. Therefore, to meet this need, the performance of LSIs (Large-Scale Integrated devices) that include analog and digital circuits on the same chip needs to be enhanced while keeping or decreasing their fabrication cost.
With popular analog/digital composite LSIs designed for this purpose, the CMOS (Complementary Metal-Oxide-Semiconductor) configuration is applied to the digital circuits capable of high-speed operation and at the same time, high-performance bipolar transistors are used for the analog circuits capable of high-frequency operation. The analog circuit needs to operate at high frequencies such as several hundreds megahertz (MHz) to several gigahertz (GHz). From this point of view, the high-frequency characteristics of the bipolar transistors need to be improved.
One of the indices representing the performance of high-frequency bipolar transistors is the “maximum oscillation frequency”, which is given by the following equation (1).                               f          max                ≈                                            f              T                                      8              ⁢                              π                ·                                  R                  b                                ·                                  C                  cb                                                                                        (        1        )            In the equation (1), fmax is the maximum oscillation frequency (at which the high-frequency power gain is equal to unity), fT is the cut-off frequency, Rb is the base resistance, and Ccb is the collector-to-base capacitance.
As seen from the equation (1), to raise the maximum oscillation frequency fmax, it is effective to raise the cut-off frequency fT, to reduce the base resistance Rb, and/or to reduce the collector-to-base capacitance Ccb.
An example of known techniques to reduce the base resistance Rb or a bipolar transistor is disclosed in 1997 IEDM (International Electron Device Meeting) Technical Digest, pp.807-810. This technique is explained below with reference to FIGS. 1A to 1C.
As shown in FIGS. 1A and 1C, a heavily-doped, n-type buried region 203 is formed on a p-type silicon (Si) substrate 201. A n-type epitaxial region 204 is formed on the substrate 202 to cover the buried region 203. A n-type pedestal region 212 is formed in the epitaxial region 204 to be placed over the buried region 203. The pedestal region 212 has an intermediate doping concentration between the epitaxial region 204 and the buried region 203. The n-type buried region 203, the n-type epitaxial region 204, and the n-type pedestal region 212 constitute the n-type collector of a bipolar transistor.
An isolation oxide 206 is selectively formed in the surface area of the epitaxial region 204. The oxide 206 separates electrically a p-type intrinsic base region 209 and a heavily-doped, p-type diffusion region (i.e., a graft base region) 218 from a heavily-doped, n-type diffusion region (i.e., a collector extraction region) 219.
A heavily-doped, n-type diffusion region 220 is formed in the intrinsic base region 209, which forms a n-type emitter region. An emitter extraction electrode 213 is formed to contact the intrinsic base region 209 by way of a dielectric 217. A titanium silicide (TiSi2) layer 221E is formed on the electrode 313. A TiSi2 layer 221B is formed on the p-type external base region 218, which serves as a base extraction region.
As shown in FIG. 1A, which shows the layout of the respective regions or parts of the transistor, the p-type graft base region (i.e., the heavily-doped, p-type diffusion region) 218 and the TiSi2 layer 221B formed thereon are divided into two parts by the emitter extraction electrode 213 and the TiSi2 layer 221E formed thereon. Two elongated base contact sections 225, which are electrically connected to the metal wiring line for the base, are respectively contacted with the TiSi2 layers 221b at each side of the emitter extraction electrode 213. The base contact sections 225 are formed to extend along the same direction. The reference symbols 226 and 227 denote an emitter contact section and a collector contact section, respectively.
An interlayer dielectric layer 222 is formed over the whole substrate 201 to cover the bipolar transistor. The layer 222 has an emitter contact hole 224E that exposes the TiSi2 layer 221E, two base contact holes 224B that expose the corresponding TiSi2 layers 221B, and a collector contact hole 224C that exposes the TiSi2 layer 221C.
With the prior-art transistor structure of FIGS. 1A to 1C, the surface of the heavily-doped p-type diffusion region (i.e., the graft base region) 218 is covered with the TiSi2 layers 221B (which have a sheet resistance sa low as approximately 5 Ω/□) at each side of the emitter extraction electrode 213. Moreover, the metal base wiring line is connected to the graft base region 218 at each side of the emitter extraction electrode 213 by way of the contact holes 224B. Accordingly, the base resistance Rb is reduced compared with the case where the region 218 is not covered with the TiSi2 layers 221B. The above-described document, IEDM Technical Digest, shows that the maximum oscillation frequency fmax is raised up to 54 GHz if the voltage applied across the collector and emitter is 2.5 V.
Next, a method of fabricating the bipolar transistor of FIGS. 1A to 1C is explained below with reference to FIGS. 2A to 2G.
First, as shown in FIG. 2A, the heavily-doped, n-type buried region 203 is formed on the p-type substrate 201 and then, the n-type epitaxial region 204 is formed to cover the region 203 by known methods. The thickness of the region 204 is set at 1 μm, for example.
Next, as shown in FIG. 2B, the isolation oxide 206 is selectively formed by using the so-called LOCOS (LOCal Oxidation of Silicon) method. A first oxide layer 205 with a thickness of 12 nm is formed to cover the epitaxial region 204 and the isolation oxide 206.
As shown in FIG. 2C, the heavily-doped n-type diffusion region (i.e., the collector extraction region) 219 is formed by ion implantation of phosphorus (P). The intrinsic base region 209 is formed by ion implantation of boron (B) at an acceleration energy of 7 keV.
As shown in FIG. 2D, a window for forming the emitter region is formed in the first oxide layer 205 and then, the pedestal region 212 is formed by ion implantation of phosphorus at an acceleration energy of 550 keV. A n-type polysilicon layer (thickness: 250 nm) doped with arsenic (As) is formed and patterned, forming the emitter extraction electrode 213.
As shown in FIG. 2E, the sidewall oxides 217 are formed by a silicon dioxide layer (thickness: 150 nm). Using the sidewall oxides 217 and the emitter extraction electrode 213, the heavily-doped, p-type diffusion region (i.e., the graft base region) 218 is formed in self-alignment to the electrode 213 by ion-implantation of boron at 10 keV. Thereafter, an RTA (Rapid Thermal Annealing) process is carried out at 1025° C. for 20 seconds, thereby diffusing the arsenic (As) atoms from the electrode 213 into the intrinsic base region 209. Thus, the n-type emitter region 220 is formed in self-alignment.
Thereafter, as shown in FIG. 2F, using known silicide technique, the surface areas of the second conductor 213, the extrinsic base region 218, and the collector extraction region 210 are subjected to silicidation reaction. Thus, the TiSi2 layers 221E, 221B, and 221C are formed.
As shown in FIG. 2G, using known technique, the interlayer dielectric layer 222 is formed to cover the transistor. The contact holes 224E, 224B, and 224c are formed by known techniques and then, tungsten (W) and Ti/TiN barrier metal layers are formed on the layer 222 and patterned, thereby forming the contact plugs 225E, 225B, and 225E in the respective contact holes 221E, 221B, and 221C.
Finally, a metal layer is formed on the interlayer dielectric layer 222 and patterned, thereby forming the emitter, base, and collector wiring lines 224E, 224B, and 225C. These lines 224E, 224B, and 225C are contacted with the plugs 225E, 225B, and 225E, respectively. With the above-explained prior-art bipolar transistor, the following problem occurs. Specifically, the position of the contact plugs 225B for the base is determined according to the interval between the emitter wiring line 224E and the base wiring line 224B. In other words, the contact holes 225B for the base are entirely overlapped with the graft base region 218. Therefore, the graft base region 218 will occupy a wide area. For this reason, it is difficult to make the maximum oscillation frequency fmax higher than the conventional bipolar transistors with the emitter/base double-polysilicon structure.
Since the maximum current for the base metal line 224B is usually as large as several hundreds microamperes (μA), the line 224B can be designed as the minimum width according to the design rule of bipolar transistors. Unlike this, the maximum currents for the emitter and collector metal lines 224B and 224C are usually as large as several tens milliamperes (mA), which is hFE times (typically, approximately 100) the maximum current for the base line 224B. Here, hFE is defined as hFE=IC/IB≈IE/IB, where IC is the collector current, IB is the base current, and IE is the emitter current. Therefore, from the viewpoint of reliability, the line 224E and 224C need to be designed considerably wider than the minimum width according to the design rule.
With the above-described prior-art transistor, the base and collector contact plugs 225B and 225C are positioned corresponding to the large widths of the emitter and collector metal lines 224E and 224C. Thus, the base contact plugs 225B are likely to be positioned at a considerable distance from the emitter extraction electrode 213.
Moreover, it the distance between the isolation oxide 206 and the base contact section 225 is reduced to narrow the graft base region 218, the isolation oxide tends to be partially broken to thereby cause short-circuit between the base and collector. This is because if placement error occurs in the contact-hole formation process, the isolation oxide will be etched and desired isolation characteristics will not be available. As a result, it is impossible to reduce the distance between the isolation oxide 203 and the base contact section 225.